ADSL is a modem technology that converts existing telephone lines into access paths for multimedia and high speed data communications. ADSL utilizes advanced digital signal processing and creative algorithms to squeeze greater amounts of information through twisted-pair telephone lines than was conventionally feasible. The ADSL standard calls for a specifically designed modem at each end of a twisted pair copper line, one at a home and the other at a central office of the phone company. Although the conventional telephone voice circuit has only a 4 KHZ bandwidth, the physical wire connection bandwidth is more than 1 MHZ.
ADSL exploits the extra bandwidth to send data to the central office where it can connect to a phone company's high capacity fiber optic network. ADSL modems increase the amount of information that conventional phone lines can carry buy using discrete multi-tone technology (DMT). DMT divides the bandwidth into independent subbands, then transmits data on all of the subbands simultaneously. Echo cancellation techniques allow upstream and downstream data to overlap. The standard also reserves a 4 KHZ region at the DC end of the frequency band for POTS (i.e., Plain Old Telephone System). ADSL is particularly attractive for consumer Internet applications where most of the data traffic is downloaded to the customer. Upstream bandwidth for uploading data can be reduced to increase downstream bandwidth since most Internet traffic is downstream.
Terminals employed at the central office typically communicate over several channels. These terminals employ modems or other communication devices for data transmissions. These modems or other communication devices can employ a digital processor, a coder/decoder component, line drivers and other peripheral devices to support transmitting and receiving of analog signal transmissions. The central office line driver drives the ADSL signal onto telephone lines. The ADSL signal includes data streams that are carried over tones that are amplitude, phase modulated and frequency separate by 4 KHZ. Generally, the tones are limited in amplitude, for example, to 3.162 VRMS with a average peak value of +/−4.47 volts. Occasionally, the amplitudes of the ADSL signal line up to generate a large peak voltage that can be 5 to 7 times larger than the RMS value. Therefore, the line driver needs to support a voltage swing that encompasses the high peak-to-average ratio. Using a standard class AB amplifier would be inefficient due to the large power supply voltages (e.g., +/−15 volt supply) needed to provide the large voltage swing to support the occasional large peak voltages. Therefore, a class G amplifier is employed that switches between high and low supply rails as the amplitude transitions between the large peak signal and the general RMS value signal.
FIG. 1 illustrates a conventional class G linear BJT amplifier 10 with class G output transistors Q1 and Q2 connected common collector. The amplifier 10 includes a positive side level shifter 12 and a negative side level shifter 14. The positive side level shifter 12 and the negative side level shifter 14 detect transitions of an ADSL input signal TXIN between a general RMS amplitude level and a high spike peak voltage. The amplifier 10 includes a positive side NPN BJT transistor Q1 and a negative side PNP BJT transistor Q2 enabled by the positive side level shifter 12 and the negative side level shifter 14, respectively, upon detection of a high spike peak voltage on the ADSL input signal TXIN. A positive side zener diode 18 is coupled to the positive side power rail of the downstream driver 16, and a negative side zener diode 20 is coupled to the negative side power rail of the downstream driver 16.
If the input signal has a general RMS amplitude level, the positive side power rail of the differential driver 16 is supplied with a low power supply voltage VCCL through the positive side zener diode 18, and the negative side power rail of the differential driver 16 is supplied with a low power supply voltage VEEL through the negative side zener diode 20. If the level shifter 12 and the level shifter 14 detect a high spike peak voltage amplitude level in the ADSL input signal TXIN, the level shifters 12 and 14 turn on the transistors Q1 and Q2, respectively. The positive side power rail of the differential driver 16 is supplied with a high power supply voltage VCCH through the positive side transistor Q1, and the negative side power rail of the differential driver 16 is supplied with a high power supply voltage VEEH through the negative side transistor Q2. The linear amplifier 10 drives the collectors of the downstream signal output drive transistors with a level shifted and half wave rectified version of the output signal.
The linear BJT amplifier 10 requires a large power supply overhead voltage to keep the class G output BJTs Q1 and Q2 from saturating. This voltage is typically about 2.5 volts at maximum downstream signal power. This is inefficient because the full load current at peak is passed through the output transistors Q1 and Q2 giving a power loss of 2.5*IPEAK. If the output transistors saturates, the transistor current gain is reduced and additional input current is required to maintain the same output current. Therefore, the supply voltages need to be about 2.5 volts higher than the rail voltages supplied to the differential driver 16 for a given output signal. Additional losses occur due to the level shifters 12 and 14, since the level shifters 12 and 14 remain on at all times to detect the transitions of the ADSL input signal TXIN between the general RMS amplitude level and the high spike peak voltage. As illustrated in FIG. 1, currents ICC1, ICC2, IEE1, and IEE2 are supplied by the power supplies to the level shifters at all times, so that transitions between amplitude levels can be detected.